In general terms, ferroelectric capacitors are comprised of a ferroelectric layer sandwiched between two electrodes. The ferroelectric layer may be comprised of, for example, PZT, SBT or BLT. For horizontal ferroelectric capacitors, the layers are stacked in a horizontal manner starting with a lower electrode at the bottom followed by the ferroelectric layer and an upper electrode at the top. On the other hand, for a vertical ferroelectric capacitor structure, the electrodes are arranged vertically with the ferroelectric layer between two vertical electrodes A cross-sectional view of a conventional vertical ferroelectric capacitor is illustrated in FIG. 1. The vertical ferroelectric capacitor 1 includes a stack 20 comprised of a ferroelectric layer 2 sandwiched between a bottom insulating layer 4 and a top insulating layer 6, the vertical electrodes 16 (only one of which is shown in FIG. 1) are located on the sidewalls of the stack. The capacitor structure 1 is mounted on a substrate. In FIG. 1, the substrate is comprised of an interlayer dielectric layer 8 deposited over a semi-conductor substrate 10 such as Si. The semiconductor substrate 10 can be prepared with electrical components such as CMOS devices and the capacitor structure is connected to these devices via contact plugs (not shown) formed in the interlayer dielectric layer. Alternatively, the capacitor can also be formed on the semiconductor substrate without an interlayer dielectric layer. As shown in FIG. 1, the capacitor 1 is covered with an interlayer dielectric hard mask 12, normally Tetraethyl Orthosilicate (TEOS), and the capacitor is shaped according to the hard mask using an RIE (reactive ion etch) process to define the shape of the capacitor. As the etching process cuts through the ferroelectric layer 2, the side faces 14 of the capacitor exposed by the etching process are damaged by the etching gas and the ions. In particular, near the faces 14 exposed by etching, the ferroelectric layer will lose oxygen and maybe lead, and it may also change phase from crystalline to amorphous. Both of these defects are detrimental to the characteristics of the capacitor, and especially so for the vertical capacitor where the area exposed to the etching process is larger.
The conventional method of compensating for such damage is to deposit the electrodes 16, comprised of conductive material such as platinum, over the damaged surfaces 14 (only one of which is shown in FIG. 1) after the etching process. The device 1 is then heated in an oxygen atmosphere using a recovery annealing process. Oxygen seeps through the platinum layer 16 into the damaged wall faces 14 of the ferroelectric layer 2 and replaces the oxygen lost in the etching process and tends to reverse the phase change. However, there is no replacement for the loss of other elements, such as lead, so the compensation is only partial.
In view of the foregoing problems with conventional processes and devices, a need exists for a method for improved compensation for damage to a capacitor during the RIE process.